RegViz: Visualize IFWCST

Silicon Labs /SiM3_NRND /SIM3U166_B /EMIF_0 /IFWCST_1

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Interpret as IFWCST_1

CSWDH=LOW, WRWAH=LOW, OEWDW=LOW, OEWAH=LOW, OEWAS=LOW, ALEWAS=LOW, WRWDW=LOW, ALEWDW=LOW, ALEWDH=LOW, WRWAS=LOW, CSWAH=LOW, WRWDH=LOW, OEWDH=LOW, CSWDW=LOW, ALEWAH=LOW, CSWAS=LOW

Description

Interface Write Control States

Fields

CSWAS	Chip Select Write Address Setup State. 0 (LOW): Set chip select (CSx) to low during the write address setup state. 1 (HIGH): Set chip select (CSx) to high during the write address setup state.
CSWAH	Chip Select Write Address Hold State. 0 (LOW): Set chip select (CSx) to low during the write address hold state. 1 (HIGH): Set chip select (CSx) to high during the write address hold state.
CSWDW	Chip Select Write Data Wait State. 0 (LOW): Set chip select (CSx) to low during the write data wait state. 1 (HIGH): Set chip select (CSx) to high during the write data wait state.
CSWDH	Chip Select Write Data Hold State. 0 (LOW): Set chip select (CSx) to low during the write data hold state. 1 (HIGH): Set chip select (CSx) to high during the write data hold state.
OEWAS	Output Enable Write Address Setup State. 0 (LOW): Set output enable (/OE) to low during the write address setup state. 1 (HIGH): Set output enable (/OE) to high during the write address setup state.
OEWAH	Output Enable Write Address Hold State. 0 (LOW): Set output enable (/OE) to low during the write address hold state. 1 (HIGH): Set output enable (/OE) to high during the write address hold state.
OEWDW	Output Enable Write Data Wait State. 0 (LOW): Set output enable (/OE) to low during the write data wait state. 1 (HIGH): Set output enable (/OE) to high during the write data wait state.
OEWDH	Output Enable Write Data Hold State. 0 (LOW): Set output enable (/OE) to low during the write data hold state. 1 (HIGH): Set output enable (/OE) to high during the write data hold state.
WRWAS	Write Signal Write Address Setup State. 0 (LOW): Set write signal (/WR) to low during the write address setup state. 1 (HIGH): Set write signal (/WR) to high during the write address setup state.
WRWAH	Write Signal Write Address Hold State. 0 (LOW): Set write signal (/WR) to low during the write address hold state. 1 (HIGH): Set write signal (/WR) to high during the write address hold state.
WRWDW	Write Signal Write Data Wait State. 0 (LOW): Set write signal (/WR) to low during the write data wait state. 1 (HIGH): Set write signal (/WR) to high during the write data wait state.
WRWDH	Write Signal Write Data Hold State. 0 (LOW): Set write signal (/WR) to low during the write data hold state. 1 (HIGH): Set write signal (/WR) to high during the write data hold state.
ALEWAS	Address Latch Enable Write Address Setup State. 0 (LOW): Set address latch enable (ALEm) to low during the write address setup state. 1 (HIGH): Set address latch enable (ALEm) to high during the write address setup state.
ALEWAH	Address Latch Enable Write Address Hold State. 0 (LOW): Set address latch enable (ALEm) to low during the write address hold state. 1 (HIGH): Set address latch enable (ALEm) to high during the write address hold state.
ALEWDW	Address Latch Enable Write Data Wait State. 0 (LOW): Set address latch enable (ALEm) to low during the write data wait state. 1 (HIGH): Set address latch enable (ALEm) to high during the write data wait state.
ALEWDH	Address Latch Enable Write Data Hold State. 0 (LOW): Set address latch enable (ALEm) to low during the write data hold state. 1 (HIGH): Set address latch enable (ALEm) to high during the write data hold state.

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